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vpfe reg  

2009-11-10 14:18:15|  分类: v4l2 |  标签: |举报 |字号 订阅

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4.4.4.3 Bitmap Window Blending and Transparency

 Bitmap  Transparency and Blending Settings
Transparency     Blending  Factor
OSDWINnMD.TEn    OSDWINnMD.BLNDn    OSD Window Contribution     Video Contribution
  OFF                                                              1
                                         1/8                       7/8
                                         2/8                       6/8
                                         3/8                       5/8
                                         4/8                       4/8
                                         5/8                       3/8
                                         6/8                       2/8
                                                                  0
  ON                              If pixel value is equal to 0:
                                                                 1
                                         1/8                       7/8
                                         2/8                       6/8
                                         3/8                       5/8
                                         4/8                       4/8
                                         5/8                       3/8
                                         6/8                       2/8
                                                                 0
                              If pixel value is not equal to 0:
                                                                 0

 

4.4.4.4 Attenuation in Bitmap Window (RGB Mode Only)

Expansion and Anti-Flicker Filters for Video Window Registers
Register.Field Description
EXTMODE.ATENOSD0EN Bitmap Window 0 RGB attenuation enable
EXTMODE.ATENOSD1EN Bitmap Window 1 RGB attenuation enable

RGB Control Registers
Control Register Window
OSDWIN0MD.BMP0MD Defines data source format for Bitmap Window 0
OSDWIN1MD.BMP1MD Defines data source format for Bitmap Window 1
TRANSPVALL.RGBL Transparency value (RGB565) for RGB565 data, or lower 16-bit of
transparency value (GB) for RGB888.
TRANSPVALU.RGBU Transparency value upper byte (R) for RGB888.

 

 4.4.4.7 OSD Bitmap Window —YUV422 Format

 4.4.4.8 OSD Attribute Window

OSD Attribute Pixel Format
Bit 3 Bit 2 Bit 1 Bit 0
Blink Enable Blend factor
0: No blink
1: Blink

 

OSD Blink Attribute Control Registers
Control Register.Field                          Description
OSDATRMD.BLNK                       Enable blinking defined by attribute window
OSDATRMD.BLNKINT                          Set the blink interval

4.4.5 OSD – Cursor Window

OSD Cursor Window Control Registers
Control Register Description
RECTCUR.RCAD Cursor color address (offset into CLUT)
RECTCUR.CLUTSR Cursor CLUT selection (RAM or ROM)
RECTCUR.RCHW Rectangular Cursor Horizontal Width
RECTCUR.RCVW Rectangular Cursor Vertical Width

4.5 Video Encoder Module

4.5.1 Video Timing Mode

     支持两种时序模式:standard NTSC/PAL 及 non-standard (user-defined).

4.5.1.1 Standard Mode

    支持的格式为 525/60 Hz (NTSC-M) or 625/50 Hz (PAL-B/D/G/H/I) for SDTV,LCD同步输出(模拟的镜像)

4.5.1.2 Nonstandard Mode

    用户定义时序,VMOD.VMD = 1.

4.5.2 Synchronous Mode

    master and slave,可用在以上两种时序模式

  4.5.2.1 Master Mode :VENC产生时序

  4.5.2.2 Slave Mode

         SYNCCTL.EXSYNC=0,HSYNC/VSYNC/FIELD引脚信号作为外部同步信号。(VIDCTL.SYDIR=1使引脚为输入)

        SYNCCTL.EXSYNC=1,用CCDC控制器作外部同步信号,使CCD timing and video timing同步,可用 使EXHIV, EXVIV,and EXFIV fields in the SYNCCTL register反转

 

                               Supported TV Formats
VMD            TVTYP        ITLC         ITLCL            NSIT            Video Format
                                                                NTSC
                                                                Non-interlace

                                                                         262   line/field
                                                            Non-interlace
                                                                          263 line/field
                                                                   PAL
                                                              Non-interlace
                                                                           312 line/field
                                                              Non-interlace
                                                                           313 line/field
                                                               Progressive
                                                                Interlace
                                                                 Interlace

                                                                          (FIELD  low fix)

 =========================================================================================

4.5.4 Digital LCD Controller

4.5.4.1 Digital Video Output Mode

VMOD.VDMD:0 =YCC16;1=YCC8;2=PRGB;3=SRGB

4.5.4.2 Timings

                                 Timing Control Registers
Register                           Description                                   Unit(1)
HSPLS                             HSYNC pulse width                               CLK
VSPLS                             VSYNC pulse width                             H (0.5H)
HINT                              HSYNC interval (HINT + 1). Must be even         CLK

                      when OSD clock is 1/2 VENC clock (standard CLK timing)
HSTART                            Horizontal data valid start position            CLK
HVALID                            Horizontal data valid duration                  CLK
VINT                              VSYNC interval (VINT + 1)                     H (0.5H)
VSTART                            Vertical data valid start position               H
VSTARTA                           Vertical data valid start position

                                 (optionally available only for even field).       H
VVALID                           Vertical data valid duration H
HSDLY                             HSYNC delay CLK
VSDLY                             VSYNC delay CLK

=============================================================================================

 当在interlaced mode (VMOD.NSIT = 1 or NTSC/PAL),VSTART 设定奇数场起始位置,VSTARTA设定偶数

场起始位置。HSYNC and VSYNC,FIELD可以通过HSDLY and VSDLY,VSDLY来设定DELAY

 当在standard mode  (VMOD.VMD = 0),水平,垂直脉宽及内部时序是固定的,以上表内HSPLS, VSPLS, HINT, and VINT参数无效。但可设置SYNNCTL.SYSW使它们有效。

                       Standard Video Timing
                                 SDTV (HDMD = 0)
                           NTSC              PAL
Parameter              (TVTYP = 0)       (TVTYP = 1)                     Unit
HSYNC pulse width          127               127                          CLK
VSYNC pulse width                                                    H
Horizontal interval        1716              1724                         CLK
Vertical interval          262.5             312.5                         H

4.5.4.3 Slave Mode Timings

4.5.4.3.1 Slave Mode Sync Path Using VPFE

4.5.4.3.2 Horizontal Timing

          此时HSTART意义与MASTER时不同,是在外部HSYNC开始19CLK后开始计算

4.5.4.3.3 Vertical Timings

4.5.4.3.4 Slave Mode Field Detection

         slave interlace mode,需进行外部FIELD detect,一般有四种方式

        · Latch FIELD input at VSYNC rise edge
        · Use raw FIELD input
        · Use VSYNC input as FIELD
        · Detect VSYNC phas

 4.5.4.4 DCLK Generator

       DCLK is output from the VCLK pin.

 

 

 

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