注册 登录  
 加关注
   显示下一条  |  关闭
温馨提示!由于新浪微博认证机制调整,您的新浪微博帐号绑定已过期,请重新绑定!立即重新绑定新浪微博》  |  关闭

liuyue18301的个人主页

追逐梦想 光辉岁月

 
 
 

日志

 
 

vpfe REG  

2009-11-10 14:17:42|  分类: v4l2 |  标签: |举报 |字号 订阅

  下载LOFTER 我的照片书  |

1.PINMUX1

22 VCLK Enable VCLK
    0 VCLK
    1 GIO[68]
21-20 EXTCLK Enable EXTCLK (Video Out pin mux)
    0 GIO[69]
    1h EXTCLK
    2h B2
    3h PWM3
19-18 FIELD Enable FIELD (Video Out pin mux)
    0 GIO[70]
    1h FIELD
    2h R2
    3h PWM3
17 DCLD Enable DLCD signal output (Video Out pin mux)
    0 LCD_OE or BRIGHT (set by LDCOUT.OES)
    1 GIO[71]
16 HYSYNC Enable HVSYNC (Video Out pin mux)
    0 HVSYNC and VSYNC
    1 GIO[73:72]
15-14 COUT_0 Enable COUT[0] (Video Out pin mux)
    0 GIO[74]
    1h COUT[0]
    2h PWM3
13-12 COUT_1 Enable COUT[1] (Video Out pin mux)
    0\ GIO[75]
    1h COUT[1]
    2h PWM3
    3h Reserved
11-10 COUT_2 Enable COUT[2] (Video Out pin mux)
    0 GIO[76]
    1h COUT[2]
    2h PWM2
    3h RTO3
9-8 COUT_3 Enable COUT[3] (Video Out pin mux)
    0 GIO[77]
    1h COUT[3]
    2h PWM2
    3h RTO2
7-6 COUT_4 Enable COUT[4] (Video Out pin mux)
    0 GIO[78]
    1h COUT[4]
    2h PWM2
    3h RTO1

5-4 COUT_5 Enable COUT[5] (Video Out pin mux)
    0 GIO[79]
    1h COUT[5]
    2h PWM2
    3h RTO0
3-2 COUT_6 Enable COUT[6] (Video Out pin mux)
    0 GIO[80]
    1h COUT[6]
    2h PWM1
    3h Reserved
1-0 COUT_7 Enable COUT[7] (Video Out pin mux)
    0 GIO[81]
    1h COUT[7]
    2h PWM0
    3h Reserved

 

 3 VPBE Integration

    VPBE实则是一个DMA主控器

    VPBE不用时可让VPSSCLK.CLKCTRL.VPBE_CLK禁用,但若使用,则应先打开,再进行其它操作

3.1.1.4 VPSS Clock Mux Control Register (VPSS_CLK_CTRL)

    6-5 VENC_CLK_SRC    27 MHz input source
         0 PLL1 divided down
         1 (EXTCRYSTAL2) External crystal 2
         2h (EXTCRYSTAL1) External crystal 1
         3h Reserved
    4 DACCLKEN Video DAC clock enable
         0 Disabled
         1 Enabled
    3 VENCLKEN VPBE/Video encoder clock enable
         0 Disabled
         1 Enabled
    2 PCLK_INV Invert VPFE pixel clock (PCLK)
         0 Disable VENC clock mux and CCDC receive normal PCLK
         1 Enable VENC clock mux and CCDC receive inverted PCLK
   1-0 VPSS_MUXSEL 0-3h VPSS clock selection
         0 Use input set by VENC_CLK_SRC (typically 27 MHZ).
         1h Reserved
         2h EXTCLK mode. Use external VPBE clock input (DAC clock = EXTCLK).
         3h PCLK mode. Use PCLK from VPFE (DAC clock = off).

 

3.1.1.5 MXI2 Oscillator Power Control:USB Physical Control Register (USB_PHY_CTRL)

   11 DATAPOL USB PHY data polarity inversion
         0 USB PHY data polarity, no inversion
         1 USB PHY data polarity inversion
 10 - 9 PHYCLKSRC USB PHY input clock source
         0 24 MHz directly from crystal
         1h 12 MHz (after dividing 36 MHz crystal by 3)
         2h {PLLCTRL1.SYSCLK3) backup in case 27 MHz crystal is used.
         3h Reserved
    8 PHYCLKGD USB PHY power and clock good
        0 BAD - PHY power not ramped or PLL not locked
        1 GOOD - PHY power is good and PLL is locked
    7 SESNDEN Session end comparator enable
        0 DISABLE - Comparator disabled
        1 ENABLE - Comparator enabled
    6 VBDTCTEN VBUS comparator enabled
        0 DISABLE - Comparators (except session end) disabled
        1 ENABLE - Comparators (except session end) enabled
    5 VBUSENS OTG analog block VBUSSENSE output status
        0 ABSENT - VBUS not present (<0.5 V)
        1 PRESENT - VBUS present (>0.5 V)
    4 PHYPLLON USB PHY PLL suspend override
        0 Normal PLL operation
        1 Override PLL suspend state
    3 Reserved Reserved
    2 VPSS VPSS oscillator power down controlOSCPDWN

         0 VPSS MXI2 powered on
         1 VPSS MXI2 power off
    1 OTGPDWN USB OTG analog block power down control
       0 OTG analog block powered on
       1 OTG analog block power off
    0 PHYPDWN USB PHY power down control
       0 PHY powered on
       1 PHY power off

 3.1.2 Resets

    不要用SyncReset or SwRstDisable states of the PSC

 3.3 Video DAC Configuration

     在SYSTEM MODULE中VDAC_CONFIG 值,推荐:

     · TRESB4R4 = 0x3
     · TRESB4R2 = 0x8
     · TRESB4R1 = 0x8
     · TRIMBITS = 0x34
     · PWD_BGZ = 1 (power-up VREF)
     · SPEED = 1 (faster)
     · PWD_VBUFZ = 1 (power-up video buffer)
     · ACCUP_EN = 0 (default 1)
     · DINV = 1 (invert)

3.3.1 Video DAC Configuration Register (VDAC CONFIG)

    29-26 TRESB4R4 Resistance trimming control bit for VREF
    25-22 TRESB4R2 Resistance trimming control bit for VREF
    21-18 TRESB4R1 Resistance trimming control bit for VREF
    17-11 TRIMBITS PNP transistor trimming control bit for VREF
    10 PWD_BGZ Power Down of VREFF
       0 power down
       1 power Up
    9 SPEED Faster operation of VREF transfer
      0 Normal
      1 Faster
    8 TVINT TV cable connect status from DAC
      0 Cable connected
      1 Cable disconnected
    7 PWD_VBUFZ Power down of video buffer
      0 Power Down
      1 Power UP
   6-4 VREFSET VREF setting to vedio buffer
   3 ACCUP_EN AC capacitor coupling externally to video buffer
      0 Disable the coupling
      1 Enable the coupling
   2 DINV Data invert from VENC (inside the DAC)
      0 No inversion - use only when VDAC is used without VREF and buffer
      1 Inversion _ When VDAC is used with VREF and buffer
   1 RESERVED Reserved
   0 RESERVED Reserved

 4.3 Master/Slave Mode Interface

    Master Mode Configuration Registers
Acronym        Register
HSPLS        Horizontal sync pulse width
VSPLS        Vertical sync pulse width
HINT         Horizontal interval
HSTART       Horizontal valid data start position
HVALID       Horizontal data valid range
VINT         Vertical interval
VSTART       Vertical valid data start position
VVALID       Vertical data valid range
HSDLY        Horizontal sync delay
VSDLY        Vertical sync delay

 4.4.1 Video Window Constraints

1.用VIDEO WINDOW0作HD显示

2.当VIDEO WINDOW0作HD显示时,VIDEO WINDOW1禁用

4.4.2.1 DDR Addresses

          OSD SDRAM Address Registers
SDRAM Address Register            Window
VIDWIN0ADL                   Video window 0 address (low 16 bits)
VIDWIN1ADL                   Video window 1 address (low 16 bits)
VIDWINADH                    Video window addresses (upper bits)
OSDWIN0ADL                   OSD bitmap window 0 address (low 16 bits)
OSDWIN1ADL                   OSD bitmap window 1/attribute window address (low 16 bits)
OSDWINADH                    OSD bitmap window addresses (upper bits)

4.4.2.2 DDR Offsets

显示区域的每行尺寸偏移,可行显示一个影像的子集(部分)

         OSD SDRAM Offset Registers
SDRAM Address Register            Window
VIDWIN0OFST               Video Window 0 SDRAM offset register
VIDWIN1OFST               Video Window 1 SDRAM offset register
OSDWIN0OFST               OSD Bitmap Window 0 SDRAM offset register
OSDWIN1OFST               OSD Bitmap Window 1/Attribute Window SDRAM offset register

 4.4.2.3 Window Positioning

1. BASEP_X and BASEP_Y 以HD,VD前沿为参考点

2. 当VENC为INTERFACE (交错模式),则YP,YL的定义为每FIELD的行数;若为PROGRESSIVE则定义为第FRAME的行数。

              OSD Window Positioning Registers
Window Positioning Registers                          Window
VIDWIN0XP                           Video Window 0 start position and size registers
VIDWIN0YP
VIDWIN0XL                           行像素
VIDWIN0YL                           行数

====================================================================================
VIDWIN1XP                           Video Window 1 start position and size registers
VIDWIN1YP
VIDWIN1XL
VIDWIN1YL

======================================================================================
OSDWIN0XP                           OSD Bitmap Window 0 start position and size registers
OSDWIN0YP
OSDWIN0XL
OSDWIN0YL
OSDWIN1XP              OSD Bitmap Window 1/Attribute Window start position and size registers
OSDWIN1YP
OSDWIN1XL
OSDWIN1YL

======================================================================================
CURXP Hardware cursor start position and size registers
CURYP
CURXL
CURYL

4.4.2.4 Window Mode – Field/Frame 

         OSD Field/Frame Mode Registers
Register.Field                       Description
VIDWINMD.VFF0                 Video Window 0 Field/Frame specification
VIDWINMD.VFF1                 Video Window 1 Field/Frame specification
OSDWIN0MD.OFF0                OSD Bitmap Window 0 Field/Frame specification
OSDWIN1MD.OFF1                OSD Bitmap Window 1 Field/Frame specification
OSDATRMD.OFFA                 OSD Attribute Window Field/Frame specification
(same address/offset as for OSD Bitmap Window 1)

4.4.2.4.1 Frame Mode

此时在DDR中的数据是以PROGRESSIVE模式存放。

此时VENC只能为INTERLACE,WINDOW HEIGHT=LINES/FIELD=1/2 DISPLAY HEIGHT,以2 X OFFSET 增加地址

4.4.2.4.2 Field Mode

1.VENC为INTERLACE模式,WINDOW HEIGHT=LINES/FIELD=1/2 DISPLAY HEIGHT,后FIELD重读DDR中前FIELD处地址空间数据

2.VENC为PROGRESSIVE模式,WINDOW HEIGHT=LINES/FRAME=FULL DISPLAY HEIGHT

4.4.2.5 Window Scaling

有两种方式放大:

一种是以像素COPY方,x2 and x4

另一种是以线性插值方式,x9/8 (640转720)and x3/2 (640转960)in horizontal direction and x6/5 (480转576)in vertical direction.

4.4.2.5.1 Window Zooming

在DDR中选取要放大的数据区域,在设置屏幕显示位置

OSD Window Zoom Registers
Register.              Field Description
VIDWINMD.VHZ0     Video Window 0 Horizontal Zoom
VIDWINMD.VVZ0     Video Window 0 Vertical Zoom
VIDWINMD.VHZ1     Video Window 1 Horizontal Zoom
VIDWINMD.VVZ1     Video Window 1 Vertical Zoom
OSDWIN0MD.OHZ0    Bitmap Window 0 Horizontal Zoom
OSDWIN0MD.OVZ0    Bitmap Window 0 Vertical Zoom
OSDWIN1MD.OHZ1    Bitmap Window 1 Horizontal Zoom
OSDWIN1MD.OVZ1    Bitmap Window 1 Vertical Zoom

4.4.2.5.2 Window Scaling – Square Pixels for NTSC/PAL Analog Output or Display Matching

                            Normal OSD Window Expansion Registers
Register            Field Description
MODE.VHRSZ          Video Window Horizontal 9/8 Expansion
MODE.VVRSZ          Video Window Vertical 6/5 Expansion
MODE.V0EFC          Video Window 0 smoothing filter enable (with MODE.EF)
MODE.V1EFC          Video Window 1 smoothing filter enable (with MODE.EF)
MODE.EF             Video Window smoothing filter (maximum line width is 720)
MODE.OHRSZ          Video Window Horizontal 9/8 Expansion
MODE.OVRSZ          Video Window Vertical 6/5 Expansion

                        Extended OSD Window Expansion Registers
Register.Field Description
EXTMODE.EXPMDSEL    Sets filtering mode before expansion
EXTMODE.SCRNHEXP    Global H expansion on all windows
EXTMODE.SCRNVEXP    Global V expansion for all windows
EXTMODE.OSDHRSZ15   Bitmap window 1.5x expansion if normal filtering done
EXTMODE.VIDHRAZ15   Video window 1.5x expansion if normal filtering done

4.4.2.5.3 Zoom and Expansion Filter Usage

vertical expansion filter 优先权比 vertical zoom filter高

 

4.4.2.5.4 Window Positioning Limits for When Using Horizontal Expansion

当水平Expansion时,同类型窗口有位置限制,不能随便设置

4.4.2.5.6 Vertical Boundary Processing

4.4.2.6 OSD Background Color

       OSD Background Color Registers
Register.                 Field Description
MODE.BCLUT             Selects the color lookup table to be used (ROM or RAM). Note that there
                      are two ROM tables and the selection for the other windows also applies
                      here (MISCCTL.RSEL).

MODE.CABG              Background color. 8-bit offset into color lookup table.

 

            Pixel Arrangement in the Display(SDRAM)
Left, Top
   P0       P1    P2 P3 P4 P5 P6 P7 ...

4.4.3.2 Expansion and Anti-Flicker Filter for Video Window 

Expansion and Anti-Flicker Filter for Video Window
Register.Field            Description
MODE.EF Expansion filter enable. Only use when EXTMODE.EXPMDSEL = 0
WIDWINMD.VFINV Inverts application of the two sets of expansion filter

               coefficients betweenfield 0 and field 1.
WIDWINMD.VnEFC Enables different anti-flicker coefficients for each field
EXTMODE.EXPMDSEL Extended mode expansion filtering mode select
EXTMODE.ZMFILVnVEN Extended mode - video window n vertical zoom filter type (x6/5)
EXTMODE.ZMFILVnHEN Extended mode - video window n horizontal zoom filter type
EXTMODE.EXPFILHEN Extended mode - video window horizontal expansion filter enable (x9/8, x1/5)
EXTMODE.EXPFILVEN Extended mode - video window vertical expansion filter enable (x6/5) 

4.4.3.2.2 Video Window Filtering - Vertical Direction

4.4.3.2.2.1 Vertical x1 Anti-Flicker (Expansion) Filter (Field Rate Conversion)

           (FIELD-BASED IMAGE TO DISPLAY)

                   Vertical x1 Anti-Flicker Filter Control Registers
Register Field                                        Value
WIDWINMD.FSINV                                          1
or
WIDWINMD.VFINV
=============================================================================================
WIDWINMD.VnEFC                                        0 or 1

Operation of Vertical x1 Anti-Flicker Filter Control Registers
Invert bit (VIDWINMD.VFINF or MODE.FSINV)                                       1

      Expand Filter (V)
Coefficient bit (VIDWINMD.VnEFC)                     Different (due to same field source)
         ON                                  FID = 0                      FID = 0      2
                                             FID = 1                     FID = 1      1
         OFF                                 FID = 0                     FID = 0      1
                                             FID = 1                      FID = 1      1

 

4.4.3.2.2.2 Vertical x1 Anti-Flicker (Expansion) Filter (Without Field Rate Conversion):the filtering function is not applied(不用FILER)

            FIELD-BASED IMAGE TO DISPLAY

 Operation of Vertical x1 Anti-Flicker Filter Control Registers
Invert bit (VIDWINMD.VFINF or MODE.FSINV)                                       1

Expand Filter (V)
Coefficient Bit (VIDWINMD.VnEFC)                      Same (due to different field source)
        ON                                   FID = 0                     FID = 0      1
                                             FID = 1                     FID = 1      1
        OFF                                  FID = 0                     FID = 0      1
                                             FID = 1                      FID = 1      1

4.4.3.2.2.3 Vertical x1 Anti-Flicker (Expansion) Filter (Frame Source Data Case) 

            FRAME-BASED IMAGE

  the filtering function is not applied(FILER功能不用)

Operation of Vertical x1 Anti-Flicker Filter for Frame Mode
Invert bit (VIDWINMD.VFINF or MODE.FSINV) 0 1 Expand Filter (V)
Coefficient bit (VIDWINMD.VnEFC) Different (due to same field source)
ON FID = 0 1 FID = 0 2
FID = 1 2 FID = 1 1
OFF FID = 0 1 FID = 0 2
FID = 1 2 FID = 1 1

4.4.4 Bitmap Windows

4.4.4.1 Color LookUp Tables 

       有三个LUT,两个ROM的,一个RAM的,RAM可编程,编程顺序如下:

1.  等 MISCCTL.CPBSY  清 0.
2.  写Y 及 Cb 到 CLUTRAMYCB .
3.  写Cr 及 CLUT address 到 CLUTRAMCR register. The address 为CLUT RAM中Y,CB,CR的偏移值
4. 重复以上.

                                      OSD Color Look-Up Table Registers
                          Register.Field                           Description
ROM color look-up table    MISCCTL.RSEL         Selects the ROM color look-p table to use for

                                                all options that selection select the

                                                ROM  table (0=DM270, 1=DM320)
Background color selection  MODE.BCLUT          Background CLUT selection (ROM or RAM)
                            MODE.CABG           Background CLUT selection (offset into 256-                                                bit table)
 Cursor CLUT selection     RECTCUR.CLUTSR       Cursor CLUT selection (ROM or RAM)
                           RECTCUR.RCAD         Rectangular Cursor color address within

                                                CLUT(offset into256-bit table)
Bitmap window CLUT         OSDWIN0MD.CLUTS0     Window 0 CLUT selection (ROM or RAM)
selections                 OSDWIN1MD.CLUTS1     Window 1 CLUT selection (ROM or RAM)
RAM CLUT Setup/Write       CLUTRAMYCB.Y         CLUTRAM Y (luma) value
                           CLUTRAMYCB.CB        CLUTRAM CB (chroma) value
                           CLUTRAMCR.CR         CLUTRAM CR (chroma) value
                           CLUTRAMCR.CADDR      CLUTRAM address offset (writes all values)
                           MISCCTL.CPBUSY       Indicates if busy when writing to CLUT RAM

 

 CLUT Mapping for 1-Bit, 2-Bit, or 4-Bit Bitmaps
Register.Field Color Corresponding to Bitmap Value
(n = 0 or 1 for OSD Bitmap
Window 0 or 1, respectively) 4-Bit Bitmap 2-Bit Bitmap 1-Bit Bitmap
WnBMP01.PAL00 0 0 0
WnBMP01.PAL01 1 - -
WnBMP23.PAL02 2 - -
WnBMP23.PAL03 3 - -
WnBMP45.PAL04 4 - -
WnBMP45.PAL05 5 1 -
WnBMP67.PAL06 6 - -
WnBMP67.PAL07 7 - -
WnBMP89.PAL08 8 - -
WnBMP89.PAL09 9 - -
WnBMPAB.PAL10 10 2 -
WnBMPAB.PAL11 11 - -
WnBMPCD.PAL12 12 - -
WnBMPCD.PAL13 13 - -
WnBMPEF.PAL14 14 - -
WnBMPEF.PAL15 15 3 1

 

 

 

 

 

 

 

 

  评论这张
 
阅读(372)| 评论(0)
推荐 转载

历史上的今天

评论

<#--最新日志,群博日志--> <#--推荐日志--> <#--引用记录--> <#--博主推荐--> <#--随机阅读--> <#--首页推荐--> <#--历史上的今天--> <#--被推荐日志--> <#--上一篇,下一篇--> <#-- 热度 --> <#-- 网易新闻广告 --> <#--右边模块结构--> <#--评论模块结构--> <#--引用模块结构--> <#--博主发起的投票-->
 
 
 
 
 
 
 
 
 
 
 
 
 
 

页脚

网易公司版权所有 ©1997-2018